1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a capacitor with an MIM (Metal/Insulator/Metal) structure.
2. Description of the Background Art
Conventionally, a semiconductor memory device such as a DRAM (Dynamic Random-Access Memory) is known as one of semiconductor devices. It is strongly required for such a semiconductor memory device to be reduced in size and highly integrated. As semiconductor memory devices are highly integrated, the size of a capacitor (storage node) constituting a memory cell and the distance between adjacent capacitors have been reduced. A capacitor must ensure a constant electrostatic capacitance, even though its size is reduced. Thus, a metal material such as ruthenium (Ru) has recently been used as a material of a capacitor electrode. Moreover, a capacitor with the MIM structure (hereinafter also referred to as an MIM capacitor) that uses a high dielectric film such as tantalum oxide (Ta2O5) as a capacitor dielectric film has been employed.
FIG. 31 is a schematic plan view of a conventional semiconductor device having the MIM capacitor described above. FIG. 32 is a schematic section view taken along the line XXXII—XXXII in FIG. 31. The conventional semiconductor device will be described with reference to FIGS. 31 and 32.
The semiconductor device shown in FIGS. 31 and 32 is a semiconductor memory device including a plurality of gate electrodes 103 formed to be arranged in parallel at predetermined intervals on a main surface of a semiconductor substrate 101 (see FIG. 32). Each of gate electrodes 103 forms a gate electrode of a field effect transistor constituting a memory cell, as will be described later. In addition, at a layer above gate electrodes 103, a plurality of bit lines 150 (see FIG. 31) are formed with a prescribed distance from gate electrodes 103, extending in a direction substantially perpendicular to the direction of gate electrodes 103 extending. Bit lines 150 are electrically connected to a conductive region formed on the main surface of semiconductor substrate 101 (see FIG. 32) through a conductive material embedded in bit line contacts 151. A plurality of capacitors are then arranged in a matrix between gate electrodes 103 and bit lines 150. The structure of the semiconductor device will specifically be described with reference to FIG. 32.
As shown in FIG. 32, the conventional semiconductor device includes a field effect transistor formed on the main surface of semiconductor substrate 101 and a capacitor electrically connected to source/drain regions (not shown) of the field effect transistor. Specifically, an isolation oxide film 102 is so formed on the main surface of semiconductor substrate 101 as to enclose an element-forming region. Gate electrode 103 is formed on the main surface of semiconductor substrate 101 and isolation oxide film 102 with a gate insulation film (not shown) interposed in between. An insulation film 105 is formed on an upper surface and sidewall surfaces of gate electrode 103. Moreover, though not shown, a source/drain region, i.e. a conductive region into which conductive impurities are implanted, is formed on the main surface of semiconductor substrate 101 so as to be adjacent to gate electrode 103.
A first interlayer insulation film 106 is formed on insulation film 105. In first interlayer insulation film 106, contact holes 107a, 107b reaching the main surface of semiconductor substrate 101 are formed between gate electrodes 103. Contact holes 107a, 107b are filled with poly landing pads 108a, 108b made of a conductive material such as polysilicon.
A second interlayer insulation film 109 is formed on an upper surface of first interlayer insulation film 106. In second interlayer insulation film 109, through holes 110a, 110b are formed, respectively, at regions located above poly landing pads 108a, 108b. SC (storage node contact) barrier metal plugs 152a, 152b are formed within through holes 110a, 110b so as to be in contact with poly landing pads 8a, 8b. SC barrier metal plugs 152a, 152b are made of a titanium nitride (TiN) film.
An SN interlayer insulation film 113 is formed on second interlayer insulation film 109. In SN interlayer insulation film 113, openings 114a, 114b are formed at regions located above SC barrier metal plugs 152a, 152b, respectively. SN electrodes 117a, 117b made of a ruthenium film are arranged within openings 114a, 114b. A capacitor dielectric film 118 is formed on SN electrodes 117a, 117b so as to extend from the inside of openings 114a, 114b to an upper surface of SN interlayer insulation film 113. Capacitor dielectric film 118 is made of a tantalum oxide (Ta2O5) film. A cell plate electrode 119 (CP electrode 119) is formed on capacitor dielectric film 118. A contact interlayer insulation film 120 is formed on cell plate electrode 119. Contact interlayer insulation film 120 is made of, for example, a plasma TEOS oxide film. An aluminum interconnection 121 is formed on contact interlayer insulation film 120. A passivation film 122 is formed covering aluminum interconnection 121.
FIGS. 33 to 37 are schematic section views for illustrating a manufacturing method of the conventional semiconductor device shown in FIGS. 31 and 32. The manufacturing method of the conventional semiconductor device shown in FIGS. 31 and 32 will be described with reference to FIGS. 33 to 37.
First, isolation oxide film 102 is so formed on the main surface of semiconductor substrate 101 (see FIG. 33) as to enclose the element-forming region. Then, a field effect transistor constituted by gate electrode 103 as shown in FIG. 33 and the like, and insulation film 105 are formed by a conventionally-used technique.
Thereafter, first interlayer insulation film 106 (see FIG. 33) having contact holes 107a, 107b (see FIG. 33) is formed on insulation film 105. Subsequently, a polysilicon film is so formed as to fill in contact holes 107a, 107b and to extend onto the upper surface of first interlayer insulation film 106. The polysilicon film located on the upper surface of first interlayer insulation film 106 is then removed by a CMP technique or the like to form poly landing pads 108a, 108b (see FIG. 33).
Subsequently, second interlayer insulation film 109 (see FIG. 33) is formed on first interlayer insulation film 106. Second interlayer insulation film 109 is a so-called storage node contact (SC) interlayer insulation film, the material of which may be, for example, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film. Second interlayer insulation film 109 may have a thickness of e.g. 450 nm. A resist film having a prescribed pattern is formed on second interlayer insulation film 109 by a photolithography technique. The resist film is used as a mask to partially remove second interlayer insulation film 109 by anisotropic etching such as dry etching. Thereafter, the resist film is removed. As a result, through holes 10a, 10b can be formed as shown in FIG. 33.
Next, a titanium nitride film (TiN film) is deposited by a CVD (Chemical Vapor Deposition) technique so as to extend from the inside of through holes 110a, 110b to the upper surface of second interlayer insulation film 109. A portion of the titanium nitride film located on the upper surface of second interlayer insulation film 109 is then removed by the CMP (Chemical Mechanical Polishing) technique. As a result, SC barrier metal plugs 152a, 152b made of a titanium nitride film are obtained as shown in FIG. 33.
Next, SN interlayer insulation film 113 (see FIG. 34) is formed on second interlayer insulation film 109. A BPTEOS film may be used, for example, as a material of SN interlayer insulation film 113. SN interlayer insulation film 113 may have a thickness of e.g. 1000 nm. Subsequently, a resist film having a prescribed pattern is formed on SN interlayer insulation film 113 by the photolithography technique. The resist film is used as a mask to partially remove SN interlayer insulation film 113 by anisotropic etching. Thereafter, the resist film is removed. As a result, openings 114a, 114b that expose SC barrier metal plugs 152a, 152b can be formed in SN interlayer insulation film 113 as shown in FIG. 34.
Next, as shown in FIG. 35, a Ru (ruthenium) film 127 is so formed as to extend from the inside of openings 114a, 114b to the upper surface of SN interlayer insulation film 113. Ru film 127 is formed such that a Ru film is first deposited extending from the inside of openings 114a, 114b to the upper surface of SN interlayer insulation film 113 by a sputtering technique. This Ru film may have a thickness of e.g. 20 nm. Thereafter, the CVD technique is used to continuously deposit the Ru film. Thus, Ru film 127 having a substantially uniform thickness may be formed.
Next, the CMP technique is used to partially remove Ru film 127 located on the upper surface of SN interlayer insulation film 113. As a result, as shown in FIG. 36, SN electrodes 117a, 117b made of the Ru film can be obtained.
Next, as shown in FIG. 37, capacitor dielectric film 118 is so formed as to extend from the surfaces of SN electrodes 117a, 117b to the upper surface of SN interlayer insulation film 113. A tantalum oxide (Ta2O5) film maybe used as capacitor dielectric film 118. Capacitor dielectric film 118 is formed by first depositing e.g. a tantalum oxide film to a prescribed thickness, followed by oxidation of the tantalum oxide film using ozone (O3) gas or the like for crystallization. The initially deposited tantalum oxide film may have a thickness of e.g. 12 nm. Further, for process conditions in oxidizing the tantalum oxide film described above, an atmospheric temperature may be set to 400° C. and ozone (O3) gas may be used as atmospheric gas.
The Ru film is deposited on capacitor dielectric film 118 to form cell plate electrode 119 (see FIG. 32). In addition, contact interlayer insulation film 120 (see FIG. 32) is formed on cell plate electrode 119. A BPTEOS film may be used as contact interlayer insulation film 120. An aluminum film (not shown) is formed on contact interlayer insulation film 120. A resist film having a pattern is formed on the aluminum film by the photolithography technique. The aluminum film is partially removed by etching or the like using the resist film as a mask, to form aluminum interconnection 121 (see FIG. 32). Thereafter, the resist film is removed. Passivation film 122 (see FIG. 32) is then formed to cover aluminum interconnection 121 and the upper surface of contact interlayer insulation film 120. Thus, the semiconductor device shown in FIG. 32 can be obtained.
The conventional semiconductor device shown above, however, had the problems as described below. In the oxidation process for forming capacitor dielectric film 118 shown in FIG. 37, a ruthenium film forming SN electrodes 117a, 117b that are capacitor electrodes is oxidated. When this occurrs, adhesion between SN interlayer insulation film 113 of the BPTEOS film and the ruthenium film forming SN electrodes 117a, 117b is deteriorated. This may have produced an air gap 153 between SN electrodes 117a, 117b and SN interlayer insulation film 113, as shown in FIG. 38. It is noted that FIG. 38 is a schematic section view for illustrating the problem of the conventional semiconductor device. Such air gap 153 would result in a cause of a shape defect of SN electrodes 117a, 117b. 
Furthermore, in the oxidation process, oxidation species contained in the ozone gas may reach SC barrier metal plugs 152a, 152b made of a titanium nitride film. If the oxidation species thus reaches SC barrier metal plugs 152a, 152b, SC barrier metal plugs 152a, 152b are oxidated. This causes a problem of increase of an electric resistance in SC barrier meal plugs 152a, 152b. If the electric resistance of SC barrier metal plugs 152a, 152b thus increases, the semiconductor device is prevented from performing normal operation (operation failure occurs), resulting in a defective product.